Analog & Custom Layout

Analog & Custom Layout

"Our Analog and Custom Layout team has significant exposure in different domains for quality execution"

Implementation Methodologies

Product Development Cycle

  • Device Sizing
    • Adjust transistor sizes to achieve optimized design.
    • Logical effort is a gate delay model that takes transistor sizes into account
  • Process and Mismatching Simulation
    • Process Simulation
      Global deviations of model parameters:
      1. Same change in all devices of the ASIC
      2. Worse-case corner analysis: (t)yp, (f)ast, (s)low
      3. Combined corners: process/voltage/temperature (PVT)
    • Mismatching Simulation
      Local deviations of model parameters
      1. Different change for each device of the ASIC
      2. Pelgrom Law
      3. Montecarlo statistical analysis
  • The Art of Analog Layout
    General Matching Rules
    • Unitary elements
    • Large area devices
    • Minimum distance
    • Same orientation
    • Same surrounding
    • Same symmetry

    Common Centroid Arrays
    PCell-Based Layout
    Decoupling Guidelines
  • Physical Verification
    • Geometrical Rules
    • Design Rule Checker
  • Parasitics Extraction
    • Motivation
    • Extraction Tools
  • DFM Techniques
    • Dummy filling
    • Antenna reduction
    • Metal slotting
    • Multiple contacts
    • Extra guard rings
 

Why to choose us?

After Sale Happy
Happy After-sales

Excellent Quality Service and Support Network

Experience
Experience Matters

A combined Expertise of 50+ years in the relevant Domain

Center of the excellance - Solution
Centre of Excellence

Using cutting edge Technology and Engineering Solutions

Quality Assurance
Quality Assurance

Uncompromised quality and timelines at a competitive budget