Let Yourself Glow
We have a breadth of exposure and the right focus with an eye to detail for great results. Our focus on training, and simplicity brings great and sustainable results.
Life at Chipspirit
You will be in a well-informed and collaborative environment where new ideas are encouraged and challenges are learning opportunities.
You will be able to hone your skills, grow through proper training and mentoring along with participation in open competitions at various levels.
Your efforts will always be recognized, providing perks that ease your stress and reward you for your contributions.
- A positive work environment
- Commissions and bonuses upon individual and team goal achievement
- A commitment to safety
- Cutting-edge technology
- And more!
1. PD Lead : (6-12Yrs)
Excellent Experience in Physical Design implementation.
Power estimation, planning and analysis (static and dynamic IR, EM)
Floor planning, placement & congestion, timing closure, CTS, post CTS flow of PV: DRC/LVS/ GDS checks
Experience in Physical Design implementation
Should have Played significant role in multiple tape-outs across 90-14nm designs complex block implementation.
Proficient in industry standard EDA tool flows (SNPS, CDN, Mentor)
Good verbal and written Communication skills
2. Verification Lead : (8-12Yrs)
Proven technical expert
Responsible for Functional/ Netlist Verification of complex ASIC/ SoCs
Create Testplans and Coverage plans
Develop Test bench including TB Components, functional coverage model, environment and Testcases and verify the functionality at Block and Chip level
Exposure to EDA tools viz. VCS, NC-Sim, Questasim
Good in debugging and problem solving skills
Proficient in System Verilog, SVA and C and PERL scripting
Proficient in using verification methodologies like VMM, OVM and UVM
3. RTL Design Lead : (8-12Yrs)
The person should be able to:
Lead a team of 4 to 10 members towards the full chip or IP design executions.
Architect digital SoC/IP/subsystem together with system designer's.
Lead the IP development and RTL-coding using the appropriate coding guidelines.
Design new methodologies to optimize the design and implementations.
Perform basic verification of the IP developed.
Do the required front-end to Back-end handoff of the RTL/implementations.
Make strong technical judgment and make good decisions.
The person should possess:
Strong knowledge in IC chip design methodology SoC/IP/Subsystem.
Sound knowledge of RTL design and front-end design tools and flows.
Good communication skills to work in cross functional international teams with analog, digital and software design engineers.
Linting, STA,CDC and Frontend to Backend handoff checks’ knowledge.
UPF rollup/creations is nice to have.
Understanding of Synthesis Constraint, reviews/etc.
Ability to lead and work in small and mid-size-teams.
Potentially analyzing test scripts.
Has delivered successful silicon into production.
4. FPGA / Logic Design Lead : (8-12Yrs)
Chipspirit is developing highly flexible and adaptive processing platforms for the Indian Defence establishments. For this we need the inventors in the FPGA based developments for the makeinindia initiatives.
As a Senior Engineer you will work as part of a team responsible for all phases of product development from definition to execution and Productization.
This position requires the individual to be creative, team-oriented, technology savvy, able to u-architect and lead complex designs given a high level architecture and willing to directly work with customers on new product definition.
Strong oral and written communication skills are essential
Ability to work collaboratively with other engineers and have strong influencing and leadership skills
Thorough understanding of system design aspects and its impact on performance and throughput
Experience in bringing up system solutions with multiple components, SW, HW etc
A minimum of 8+years of experience is required.
Demonstrated ability to provide technical advice, leadership, and direction to more junior engineers.
5. FPGA Designer : (8-12Yrs)
Hands-on experience in Xilinx/Altera Design tools, FPGA architecture
Experience in RTL coding using VHDL, Verilog, System Verilog and C/C++
Experience in USB protocol implementation
Experience in Cryptographic algorithms implementation with FPGA’s(AES, RC6)
RTL simulations, board level testing and debugging
Implementation of test cases for verification
Good fundamentals of logic design and RTL coding
Experience in synthesis and timing closure
Individual ownership of standalone FPGA designs
Support for HW board bring-up
Working knowledge of lab equipment such as oscilloscopes and logic analyzers.
Experience in designing FPGAs with embedded soft or hard processors, and RTOS/Petalinux.